1. Field of the Invention
The present invention relates to an apparatus and a method for verification support, and a computer product for creating verification properties used in verifying various objects, in LSI design.
2. Description of the Related Art
In the field of LSI design, while there have been demands to increase work efficiency by shortening design time, it is essential to have a verification process for verifying if each LSI works properly. Especially, because there are demands for LSIs that are large in scale, have sophisticated functions, have a high speed, and consume less electricity, it is important to have such a verification process to maintain high quality of the LSIs.
An LSI includes an asynchronous multi-clock logical circuit driven by two or more clocks with mutually different cycles. The asynchronous multi-clock logical circuit may experience a problem when data is transferred from a circuit driven by one clock to another circuit driven by another clock; in other words, when data is transferred over a border between two clock domains, due to disturbance in the value transfer caused by metastability. More specifically, the problem occurs because the value is transferred from one clock domain to another clock domain either one cycle later or one cycle earlier.
Japanese Unexamined Patent Application Publication No. H6-83901 and Japanese Unexamined Patent Application Publication No. H10-117185 disclose a verification process in which metastability is introduced in a logical circuit in a simulation or static verification environment, and it is checked whether verification properties for normal verification (i.e. no occurrence of metastability) are violated.
According to the conventional technique described above, although there are a large number of clock domains in an asynchronous multi-clock logical circuit, designers try to find manually in the clock domains, locations at which problems have been caused by metastability. Designers are also expected to analyze what types of verification processes are effective, because even if some locations have problems caused by metastability, there is no apparent change in the external ports, or sometimes the change is masked by other signals. Accordingly, there have been problems that the burden on the designers is more, the designing labor increases, and the designing period is long.